Network Software Engineer (Hardware Abstraction Layer/Linux Kernel Stack)

About this opportunity

Zhone Technologies Inc. is an innovative startup offering an exciting opportunity to be part of a dynamic network software engineering team. As a Network Software Engineer , you will be responsible for designing and implementing hardware abstraction layers (HAL) , Linux kernel components , and ASIC platform integration for next-generation network equipment.

You will work closely with architecture, platform, and hardware teams to ensure seamless integration with ASIC SDKs, optimize hardware-software interactions, and contribute to a modular, scalable system software foundation. This role reports to the Director of Software Development.

What You’ll Do

• Collaborate on high-level system and platform architecture design
• Develop and adapt HAL components for new hardware platforms (e.g., Broadcom/Marvell/VSC SDKs, SAI for SONiC)
• Integrate and validate switching ASIC SDKs with embedded system software
• Debug and resolve hardware-software interaction issues at the kernel and board level
• Contribute to SONiC platform enablement (e.g., platform.json, SAI drivers, CONFIG_DB integration)
• Write and maintain embedded Linux device drivers (I2C, SPI, PHY/MAC, LEDs, etc.)
• Assist in hardware bring-up, including bootloaders, device trees, and CPLD integration
• Optimize kernel-level performance, reliability, and interface control
• Write and execute unit, integration, and system validation tests
• Collaborate with cross-functional software and hardware teams

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
• 3+ years of experience in embedded software or platform software development
• Hands-on experience with HAL design, Linux device drivers, and low-level hardware integration
• Familiarity with Broadcom or similar switching ASICs and platform SDKs
• Understanding of Linux networking and kernel subsystems
• Proficiency in C/C++, with debugging skills in embedded environments
• Strong teamwork and communication skills
• Motivated, detail-oriented, and eager to learn

Assets You May Possess

• Hardware Abstraction Layer (HAL) & Device Driver Development
  • Solid understanding of HAL design principles and platform abstraction mechanisms
  • Experience writing and debugging drivers for:
    • I2C, SPI, EEPROM, LEDs, fans, thermal sensors
    • PHY/MAC, MDIO, SFP/QSFP, SerDes
    • PCIe, memory-mapped interfaces
• ASIC SDK & Switching Chipset Integration
  • Practical experience integrating and validating:
    • Broadcom SDK
    • Marvell Prestera SDK
    • Microchip/Vitesse VSC SDK
  • Knowledge of VLAN/FDB/port setup, initialization sequences, and platform adaptation APIs
• SONiC & SAI (Switch Abstraction Interface).
  • Familiarity with SONiC containerized architecture and platform database structure
  • Experience configuring platform files: platform.json, hwsku, platform-modules
  • Understanding of CONFIG_DB, APP_DB, STATE_DB, and SONiC build environment
  • Ability to port or extend SAI APIs for new hardware
• Hardware Bring-up & Platform Integration.
  • Experience with bootloaders (U-Boot), device tree configuration, BSP creation
  • Hardware integration: EEPROM, PSU/FAN, CPLD, LED indicators
  • Comfortable with low-speed bus interfaces: I2C, SPI, GPIO
• Hardware-Software Interaction, Debugging & Optimization.
  • Debugging link bring-up, PHY init, SerDes tuning
  • Familiar with DMA, IRQ handling, and register-level debugging
  • Tools: gdb, strace, dmesg, perf, valgrind, JTAG, oscilloscopes
• Validation & Automation.
  • Test development and scripting using Python, Bash, TCL/Expect
  • Experience building automated platform validation workflows
• Preferred / Nice to Have
  • Prior experience porting SONiC to custom hardware
  • Experience working with ASIC vendors for feature validation or hardware bug tracing
  • Familiarity with ONIE, Redfish/IPMI, or U-Boot diagnostics
  • Open-source contributions to kernel drivers, SONiC, or SAI
  • Knowledge of PTP, SyncE, or other timing protocols is a plus